The present invention relates generally to semiconductor fabrication techniques, and more particularly to methods for planarizing metal pillars which are formed over regions of the semiconductor substrate, which regions are at differing heights.
Integrated circuits are generally formed as layered structures where a plurality of insulating and conductive layers are formed over a silicon wafer substrate having numerous active regions formed thereon. As integrated circuits become increasingly complex, the density of active regions formed on the surface becomes greater and greater. One limit on the density of such features, however, is the ability to form very fine metallization lines over the insulating layers which are stacked over the substrate. To form such fine metallization lines, it is necessary that the insulating layers be planarized to present a smooth and even surface on which the lines are to be patterned. While a variety of etch-back techniques have been developed to achieve such planarization, such techniques are not always effective and there is a continuing need to improve planarization methods for particular circumstances.
The present invention is concerned primarily with the planarization of metal pillars employed as vertical interconnects between various active regions on the semiconductor substrate and an overlying metallization layer. The pillars are formed by depositing a metal layer over the substrate, and the thickness of the metal layer will be substantially the same over all flat areas of the substrate. Thus, the tops of the pillars which are subsequently formed over regions having different elevations will themselves terminate at different elevations.
For the above reasons, it is desirable to provide improved methods for planarizing metal pillars formed on semiconductor substrates, particularly where difference in height between such pillars is magnified by relatively large variations in the surface of the substrate. It would be particularly desirable if such methods were useful not only for interconnecting the substrate with an overlying metallization layer, but also for interconnecting successive horizontal metallization layers which are separated by an intermediate dielectric layer.